1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus which is tested in synchronization with an external clock.
2. Related Art
A semiconductor memory apparatus is often tested to check its normal operation. Since a semiconductor memory apparatus typically receives a clock signal and operates in synchronization with the clock signal, testing the semiconductor memory apparatus is done by inputting a clock signal from a test equipment to the semiconductor memory apparatus and then inputting and outputting test data to and from the semiconductor memory apparatus. Testing a semiconductor memory apparatus includes testing for checking normal operation of a cell, testing for checking coupling effect between adjacent metal lines, and testing for checking a margin between signals with temporal characterization.
Semiconductor memory apparatuses of these days operate at a high speed. Such high speed operation of semiconductor memory apparatuses may cause problems in testing such devices. Specifically, a semiconductor memory apparatus may be tested in a wafer level in which chips are arranged in a wafer state before being separated from one another or may be tested in a package level in which chips are separated and are coupled to a package state. In a wafer level test, a maximum frequency value of a clock signal inputted to a semiconductor memory chip by an outmoded test equipment often falls short of the value of a frequency (referred to as a ‘target frequency’) at which the semiconductor memory apparatus will operate in the packaged state, due to the high speed operation of the semiconductor memory apparatus. Therefore, characteristics of the semiconductor memory apparatus at the target frequency in the wafer level may not be properly tested. In order to cope with this problem, a conventional semiconductor memory apparatus is often tested twice: once in the wafer level for normal operations of a cell and basic characteristics, such as a current performance requirements, which may be tested at a low frequency, and the second test is performed in the package level where input/output line coupling effect and a pipe latch strobe signal timing margin are checked at the target frequency by inputting a high speed clock. However, the lack of feasible evaluation measures of operation characteristics at the target frequency in the wafer level, as in this case, means that disqualifying memory chips whose operation characteristics do not meet the performance requirements cannot be filtered in advance, and a packaging process should be performed again for such disqualifying memory chips. This leads to the decreased manufacturing yield of packages and the increased manufacturing cost. Further, in the case of a product such as a TSV (through-silicon via) product in which a plurality of wafer chips are connected in parallel, a plurality of good wafer chips may be classified as bad wafer chips, due to the presence of bad wafer chips which have not been filtered in the wafer level in advance. Moreover, when considering that a semiconductor memory apparatus may not undergo a packaging process and may be placed on a market as a wafer level product, if characteristics cannot be fully evaluated in the wafer level as described above, quality reliability of the product is likely to deteriorate. Thus, the semiconductor memory apparatus should be tested using another test equipment capable of performing a test at the target frequency even in the wafer level, which increases a manufacturing period and a manufacturing cost.
FIG. 1 is a schematic block diagram illustrating components which generate a DLL (delay-locked loop) input clock and an AC input clock, i.e., an address and command input clock, in a conventional semiconductor memory apparatus. The conventional semiconductor memory apparatus receives an external clock clk_ex through a clock buffer 1 and generates a normal clock clk_n as an internal clock signal. The normal clock clk_n is inputted to a DLL circuit unit 2 and an AC circuit unit 3. The DLL circuit unit 2 and the AC (address/command) circuit unit 3 perform operations in synchronization with the inputted normal clock clk_n. The DLL circuit unit 2 is a component which includes a delay-locked loop circuit and is configured to generate a DLL clock according to the inputted normal clock clk_n and determine a data output timing. The AC circuit unit 3 is a component which is configured to receive an address signal and a command signal from outside and generate an internal address signal and an internal command signal.